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Preliminary
RT9262/A
High Efficiency, Low Supply Current, Step-up DC/DC Converter
General Description
The RT9262/A is a compact, high efficient, step-up DC/DC converter with an adaptive current mode PWM control loop, providing a stable and high efficient operation over a wide range of load currents. It operates in both continuous and discontinuous current modes in stable waveforms without external compensation. The low start-up input voltage below 1V makes RT9262/A suitable for 1 to 4 battery cell applications providing up to 400mA output current. The 550KHz high switching rate minimized the size of external components. Besides, the 17A low quiescent current together with high efficiency maintains long battery lifetime. The 1.8V to 5V output voltage is set with 2 external resistors. Both internal 2A switch and driver for driving external power devices (NMOS or NPN) are provided. A 300mA LDO is included in RT9262 to provide a secondary low noise output as well as an output current stop in the shutdown mode. Similarly, a 1.8V to 5V LDO output voltage can be set with 2 external resistors. For RT9262A, a low battery detector with 0.86V detection voltage is included. RT9262/A are provided in SOP-8 packages.
Features
1.0V Low Start-up Input Voltage High Supply Capability to Deliver 3.3V 100mA with 1V Input Voltage 17A Quiescent (Switch-off) Supply Current 90% Efficiency 550KHz Fixed Switching Rate Providing Flexibility for Using Internal and External Power Switches Built-in 300mA LDO, also for the Zero-OutputCurrent Shutdown Mode (RT9262) Boost DC-DC Integrating LDO for Up-Down Regulation (RT9262) Built-in 0.86V Voltage Detector (RT9262A) 8-Pin SOP Package
Applications
PDA Portable Instrument Wireless Equipment DSC LCD Back Bias Circuit RF-Tags
Pin Configurations
Part Number RT9262CS (Plastic SOP-8) Pin Configurations
TOP VIEW
GND 1 EXT 2 LFB 3
8 7 6 5
CE LX VDD FB
Ordering Information
RT9262A Package type S : SOP-8 Operating temperature range C: Commercial standard A : Include low battery detector Default : Include LDO RT9262ACS (Plastic SOP-8)
LDOO 4
TOP VIEW
GND 1 EXT 2 LBO 3 LBI 4
8 7 6 5
CE LX VDD FB
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RT9262/A
Marking Information
Part Number RT9262CS RT9262ACS Marking RT9262CS RT9262ACS
Preliminary
Typical Application Circuit
VIN L1 4.7H D1
100F VDD CE 100pF EXT LX GND FB R2 980K C2 1F + C1 100F 3.3V VOUT1
RT9262
R1 1.6M
2.5V VOUT2 C3 10F +
R4 1.3M R3 680K
L DO O 1nF LFB
Fig. 1 RT9262 Typical Application for Portable Instruments below 400mA
VIN L1 4.7H D1
100F 100pF EXT LX GND FB R2 980K C2 1F + C1 100F
VDD CE Low Battery Warning Output (Open Collector) LB O R4 L BI
RT9262A
R1 1.6M
3.3V VOUT1
R3
Fig. 2 RT9262A Typical Application for Portable Instruments below 400mA
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Preliminary
RT9262/A
VIN
100F VDD 100pF EXT LX GND FB R2 980K C2 1F + C1 100F L1 4.7H D1
Chip Enable Input 3.3V VOUT + C3 10F
CE L DO O LFB
RT9262
R1 1.6M
Fig. 3 Application Circuit with Zero-Output-Current Shutdown Mode Control
VIN R1 100pF 1.6M LX EXT GND FB R2 980K C2 1F + Q1 NMOS D1 L1 4.7H
100F VDD CE
RT9262
2.5V VOUT2 C3 10F +
LDOO R4 1.3M R3 680K 1nF LFB
3.3V VOUT1
C1 100F
Fig. 4 0.4A ~ 2A Output Current Application
5V VIN 100F CE 2.5V VOUT2 C3 10F + R4 1.3M R3 680K L DO O 1nF LFB GND VDD
L1 10H
D1
RT9262
EXT LX FB
Q1 NMOS R1 2.2M R2 200K C2 1F + 0.1F
15V VOUT1
Rm 0.05 ~0.1
C1 100F
Fig. 5 High Voltage Application (Rm should be added when IL > 100mA)
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RT9262/A
Pin Description
Pin No. RT9262 1 2 3 4 RT9262A 1 2 --Pin Name GND EXT LFB LDOO
Preliminary
Pin Function Ground Output pin for driving external NMOS or NPN When driving an NPN, a resistor should be added for limiting base current. Feedback pin of the built-in LDO (Internal Vref = 0.86V) Voltage output pin of the built-in LDO Drain output pin of the NMOS of the built-in low voltage detector This pin will be internally pulled low when the voltage at LBI pin drops to below 0.86V. Input pin of the built-in low voltage detector Trip point = 0.86V Feedback input pin Internal reference voltage for the error amplifier is 1.25V. Input positive power pin of RT9262/A Pin for switching Chip enable RT9262/A gets into shutdown mode when CE pin set to low.
--
3
LBO
--
4
LBI
5 6 7 8
5 6 7 8
FB VDD LX CE
Absolute Maximum Ratings
Supply Voltage LX Pin Switch Voltage LDO Output Voltage Other I/O Pin Voltages LX Pin Switch Current EXT Pin Driver Current LBO Current Power Dissipation, PD @ TA = 25C SOP-8 * Package Thermal Resistance SOP-8, JA Operating Junction Temperature Storage Temperature Range -0.3V to 7V -0.3V to (VDD + 0.8V) -0.3V to (VDD + 0.3V) -0.3V to (VDD + 0.3V) 2.5A 30mA 30mA 0.625W 160C/W 150C -65C ~ +150C
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Preliminary Electrical Characteristics
(VIN = 1.5V, VDD set to 3.3V, Load Current = 0, TA = 25C, unless otherwise specified) Parameter Start-UP Voltage Operating VDD Range No Load Current I (VIN) Switch-off Current I (VDD) Shutdown Current I (VIN) Feedback Reference Voltage Feedback Reference Voltage for LDO LBI Pin Trip Point Switching Rate Maximum Duty LX ON Resistance Current Limit Setting EXT ON Resistance to VDD EXT ON Resistance to GND Line Regulation Load Regulation LDO PMOS ON Resistance RT9262 LDO Drop Out Voltage LBO ON Resistance CE Pin Trip Level Temperature Stability for FB, LFB, LBI Thermal Shutdown Thermal Shutdown Hysterises TS TSD TSD RT9262 RT9262A VDROP VLINE VLOAD ILIMIT RT9262 RT9262A FS DMAX Symbol VST VDD INO LOAD Test Conditions IL = 1mA Start-up to IDD1 > 250A VIN = 1.5V, VOUT = 3.3V Min -0.8 ---1.225 0.843 0.843 -----------0.2 ----
RT9262/A
Typ 0.98 -47 17 0.1 1.25 0.86 0.86 550 92 0.25 2 40 30 10 0.25 1 70 40 0.8 50 165 10
Max 1.05 6.5 --1 1.275 0.877 0.877 --------1.5 --1.4 ---*
Units V V A A A V V V KHz % A mV/V mV/mA mV V ppm/C C C
ISWITCH OFF VIN = 6V IOFF VREF VREF CE Pin = 0V, VIN = 4.5V Close Loop, VDD = 3.3V Close Loop, VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VDD = 3.3V VIN = 1.5 ~ 2.5V, IL = 1mA VIN = 2.5V, IL = 1 ~ 100mA VDD = 3.3V VDD = 3.3V, IL = 100mA VDD = 3.3V VDD = 3.3V Guaranteed by Design Guaranteed by Design Guaranteed by Design
* Note: The CE pin shall be tied to VDD pin and inhibit to act the ON/OFF state whenever the VDD pin voltage may reach to 5.5V or above.
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RT9262/A
Function Block Diagram
Preliminary
VDD LDOO LFB FB
VDD Q2 PMOS
RT9262
_ + 0.86V EXT LX
VDD 1.25V R2 CE
Loop Control Circuit
Q1 NMOS R1
Q3 Over Temp. NMOS Detector
VDD LBI LBO
Q2 NMOS
_ + 0.86V
VDD 1.25V R2 CE
Q3 Over Temp. NMOS Detector
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_
FB
_ +
Shut Down GND
RT9262A
EXT LX Loop Control Circuit Q1 NMOS R1 Shut Down GND +
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Preliminary Typical Operating Charateristics
Efficiency
VOUT = 3.3V ; TA = 25C
RT9262/A
Efficiency
VOUT= 5.0V; TA = 25C
No Load Current
90 80 70
100 140
No Load Current
TA = 25C VOUT = 3.3V
120
TA = 25C VOUT = 5.0V
60
IDD ( A)
IDD ( A)
50 40 30
80 60 40
20 10
20
Refer to Application Circuit Fig.1 and Fig.2
0 1 1.2 1.5 2 2.5 3
0 1
Refer to Application Circuit Fig.1 and Fig.2
1.2 1.5 2 2.5 3 4
Input Voltage (V)
Input Voltage (V)
Start Up Voltage
1.4
Start Up Voltage
1.25 1.20 1.15
TA = 25C 1.3 VOUT = 3.3V
Input Voltage (V)
1.2 1.1 1.0 0.9
TA = 25C VOUT= 5.0V
Input Voltage (V)
Refer to Application Circuit Fig.1 and Fig.2
1.10 1.05 1.00 0.95 0.90 0.85
0.8 0 20 40 60 80 100
Refer to Application Circuit Fig.1 and Fig.2
0.80 0 25 50 75 100
ILOAD (mA) ILOAD (mA) in constant resistance load
ILOAD (mA) ILOAD (mA) in constant resistance load
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RT9262/A
Application Note
Preliminary
Output Voltage Setting Referring to application circuits Fig.1 to Fig.5, the output voltage of the switching regulator (VOUT1) can be set with Eq.1. The LDO output voltage (VOUT2 of RT9262) can be set with Eq.2. R1 VOUT1 = (1 + ) x 1.25 V Eq.1 R2
VOUT 2 = (1 + R4 ) x 0.86 V R3
PRECAUTION 1: Improper probing to FB or LFB pin will cause fluctuation at VOUT1 and VOUT2. It may damage RT9262/A and system chips because VOUT1 may drastically rise to an over-rated level due to unexpected interference or parasitics being added to FB pin. PRECAUTION 2: Disconnecting R1 or short circuit across R2 may also cause similar IC damage as described in precaution 1. PRECAUTION 3: When large R values were used in feedback loops, any leakage in FB/LFB node may also cause VOUT1 and VOUT2 voltage fluctuation, and IC damage. To be especially highlight here is when the air moisture frozen and re-melt on the circuit board may cause several A leakage between IC or component pins. So, when large R values are used in feedback loops, post coating, or some other moisture-preventing processes are recommended.
VOUT1
Eq.2
And trip point of the low battery detector is 0.86V at LBI pin of RT9262A. Feedback Loop Design Referring to application circuits Fig.1 to Fig.5, The selection of R1, R2, R3, and R4 based on the tradeoff between quiescent current consumption and interference immunity is stated below: * Follow Eq.1 and Eq.2. * Higher R reduces the quiescent current (Path current = 1.25V/R2, and 0.86V/R3), however resistors beyond 5M are not recommended. * Lower R gives better noise immunity, and is less sensitive to interference, layout parasitics, FB/LFB node leakage, and improper probing to FB/LFB pins. * A proper value of feed forward capacitor parallel with R1 (or R4) on Fig.1 to Fig.5 can improve the noise immunity of the feedback loops, especially in an improper layout. An empirical suggestion is around 100pF ~ 1nF for feedback resistors of M, and 10nF ~ 0.1F for feedback resistors of tens to hundreds K. For applications without standby or suspend modes, lower values of R1 to R4 are preferred. For applications concerning the current consumption in standby or suspend modes, the higher values of R1 to R4 are needed. Such "high impedance feedback loops" are sensitive to any interference, which require careful layout and avoid any interference, e.g. probing to FB/LFB pins.
Prober Parasitics
_ Q +
R1 FB Pin R2
Layout Guide * A full GND plane without gap break. * VOUT1 to GND noise bypass - Short and wide connection for C2 to Pin1 and Pin6. * VIN to GND noise bypass - Add a 100F capacitor close to L1 inductor, when VIN is not an idea voltage source. * Minimized FB/LFB node copper area and keep far away from noise sources. * Minimized parasitic capacitance connecting to LX and EXT nodes, which may cause additional switching loss. * The following diagram is an example of 2-layer board layout for application circuits Fig.1 to Fig.4.
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Preliminary
RT9262/A
First Layer
RT9262/A
Second Layer (Full GND Plane)
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RT9262/A
Package Information
Preliminary
H A M
JB
F
C
D
I
Dimensions In Millimeters Symbol A B C D F H I J M Min 4.801 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 Max 5.004 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270
Dimensions In Inches Min 0.189 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 Max 0.197 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
8-Lead SOP Plastic Package
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Preliminary
RT9262/A
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RT9262/A
Preliminary
RICHTEK TECHNOLOGY CORP.
Headquarter
5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
RICHTEK TECHNOLOGY CORP.
Taipei Office (Marketing)
8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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